1. Field of the Invention
The present invention relates to a display controller for executing control for making a display unit display images in response to data which are stored in a display memory, and more particularly, it relates to a display controller for displaying images on a display unit such as an LCD (liquid crystal display) in a vertically enlarged manner.
2. Background of the Invention
For example, standards of 400 and 480 horizontal scanning lines are known as software standards in relation to screen display of a personal computer. In order to attain compatibility between these standards, it is necessary to vertically enlarge or reduce images.
FIG. 13 is a block diagram showing a conventional display controller 1 for displaying images in a vertically enlarged manner. This display controller 1 executes control for making a display unit 3 such as an LCD display images in response to data which are stored in a display memory 2. The data stored in the display memory 2 are supplied from a CPU. The storage data are read from the display memory 2 in accordance with addresses which are supplied from the display controller 1. The as-read data are processed in the display controller 1 as hereinafter described in detail, and supplied to the display unit 3 as color image data VD. The display unit 3 is also supplied with horizontal and vertical synchronizing signals HS and VS from the display controller 1. Thus, images which are responsive to the data stored in the display memory 2 are displayed on the display unit 3.
The display controller 1 comprises a horizontal counter 15, a horizontal timing generation circuit 16, a vertical counter 17 and a vertical timing generation circuit 18, as parts for generating various timing signals. The horizontal counter 15 receives a clock CC in its timing input T, while receiving a signal HE from the horizontal timing generation circuit 16 in its reset input R. The horizontal timing generation circuit 16 receives a count output from the horizontal counter 15 in its input I, and outputs the horizontal synchronizing signal HS, a signal B and the signal HE from its output Q. These signals HS, B and HE are shown in a timing chart of FIG. 14. The signal B indicates a retrace line period, and the signal HE shows the last timing of the retrace line period. Referring to FIG. 14, numerals provided on the respective pulses of the clock CC denote count values of the horizontal counter 15.
FIG. 15 is a block diagram showing the horizontal timing generation circuit 16 in detail. The horizontal timing generation circuit 16 comprises registers 161a, 161b, 161c and 161d which can be set from the exterior. A horizontal total character value A, a horizontal display end timing value B, a horizontal synchronizing signal start timing value C and a horizontal synchronizing signal end timing value D are set in the registers 161a, 161b, 161c and 161d respectively. The values A, B, C and D set in the respective registers 161a, 161b, 161c and 161d are compared with the count value of the horizontal counter 15 by comparators 162a, 162b, 162c and 162d respectively. Comparison outputs of the comparators 162a, 162b, 162c and 162d are supplied to data inputs D of D flip-flops 163, 165, 166 and 167 respectively. Timing inputs T of the D flip-flops 163, 165 and 166 are supplied with the clock CC, while a timing input T of the D flip-flop 167 is supplied with the signal HE, which is outputted from the D flip-flop 163. On the other hand, a D flip-flop 164 is supplied with the output of the D flip-flop 163 and the clock CC in its data and timing inputs D and T respectively.
Outputs of the D flip-flops 164 and 165 are supplied to set and reset inputs S and R of an RS flip-flop 168 respectively. Further, outputs of the D flip-flops 166 and 167 are supplied to set and reset inputs S and R of another RS flip-flop 169 respectively. The aforementioned values A, B, C and D are properly set so that the horizontal synchronizing signal HS and the signals B and HE are derived from the RS flip-flops 169 and 168 and the D flip-flop 163 respectively.
Referring again to FIG. 13, the vertical counter 17 receives the signal B and a signal LH from the horizontal and vertical timing generation circuits 16 and 18 in its timing and reset inputs T and R respectively. A count output of the vertical counter 17 is supplied to an input I of the vertical timing generation circuit 18, which in turn outputs the vertical synchronizing signal VS and the signal LH shown in a timing chart of FIG. 16 from its output Q. The signal LH shows the final line of one frame.
FIG. 17 is a block diagram showing the vertical timing generation circuit 18 in detail. The vertical timing generation circuit 18 comprises registers 181a, 181b and 181c which can be set from the exterior. A vertical total line value E, a vertical synchronizing signal start timing value F and a vertical synchronizing signal end timing value G are set in the registers 181a, 181b and 181c respectively. The respective values set in the registers 181a, 181b and 181c are compared with the count output of the vertical counter 17 by comparators 182a, 182b and 182c respectively. Comparison outputs of the comparators 182a, 182b and 182c are supplied to data inputs D of D flip-flops 183, 184 and 185 respectively. The D flip-flops 183, 184 and 185 are also supplied in timing inputs T thereof with the signal B from the horizontal timing generation circuit 16.
Outputs of the D flip-flops 184 and 185 are supplied to set and reset inputs S and R of an RS flip-flop 186 respectively. Thus, the respective values E, F and G are properly set in the registers 181a, 181b and 181c so that the signals VS and LH shown in the timing chart of FIG. 16 are derived from the RS flip-flop 186 and the D flip-flop 183 respectively.
Referring again to FIG. 13, the display controller 1 also comprises a head address generation circuit 10 and an address counter 11 as parts for generating addresses of the display memory 2. The display controller 1 further comprises a data skipping counter 19, an AND gate 20, and a selector 21 as parts for data-skipping a reference signal for address generation. The data skipping counter 19 is formed by a 2-bit counter in this example.
The data skipping counter 19 is supplied with the signals B and LH from the horizontal and vertical timing generation circuits 16 and 18 in its negative logic timing and reset inputs T and R respectively. The data skipping counter 19 outputs a carry signal C every time its count value reaches 3, so that the carry signal C is supplied to a negative logic input of the AND gate 20. The AND gate 20 is supplied in its another input with the signal B from the horizontal timing generation circuit 16, while its output is supplied to an A input of the selector 21. The selector 21 is supplied in its B input with the signal B from the horizontal timing generation circuit 16. The selector 21 selects the signal received in the A or B input in response to a selection signal S, to output the same.
The head address generation circuit 10 receives the signal from the selector 21 and the signal LH from the vertical timing generation circuit 18, to generate a head address of each horizontal scanning line in accordance with these signals by a predetermined rule. The address counter 11 receives the head address from the head address generation circuit 10 in its data input D. The address counter 11 further receives the signal HE from the horizontal timing generation circuit 16 and the clock CC in its load and timing inputs LD and T respectively. The address counter 11 loads the head address in response to the signal HE, and up-counts the addresses one by one from the head address in response to the clock CC. These addresses are supplied to an address input A of the display memory 2.
FIG. 18 is a block diagram showing the head address generation circuit 10 in detail. The head address generation circuit 101 comprises a start address register 101, a selector 102, a D flip-flop 103, a full adder 104, and an offset register 105. The selector 102 receives an output of the full adder 104 in its A input, while receiving a start address which is previously stored in the start address register 101 in its B input. The signal LH from the vertical timing generation circuit 18 indicating the final line of one frame is supplied to a selection input S of the selector 102, which in turn selects its B input in response to a high level of the signal LH while selecting its A input in response to a low level of the signal LH. Namely, the selector 102 outputs the start address which is stored in the start address register 101 only at the last of one frame, while outputting the output of the full adder 104 in other case. The D flip-flop 103 receives the output of the selector 102 in its data input D, to latch this signal in response to a signal which is supplied to its timing input T, i.e., a signal which is supplied to an input AL of the head address generation circuit 10 from the selector 21. The D flip-flop 103 is formed by 16 D flip-flops which are provided in parallel with each other in correspondence to a 16-bit output from the selector 102.
Each data latched in the D flip-flop 103 is outputted from an output O as the head address of each horizontal scanning line. Namely, different head addresses are successively outputted every time a signal is received in the input AL of the head address generation circuit 10 from the selector 21, i.e., every horizontal scanning line. The full adder 104 receives the output of the D flip-flop 103 in its A input, while receiving an offset value which is previously set in the offset register 105 in its B input. The full adder 104 outputs a value, which is obtained by adding the offset value stored in the offset register 105 to the currently outputted head address, as a head address for a next horizontal scanning line. This head address is latched by and outputted from the D flip-flop 103 in response to a next Al input.
FIG. 19 illustrates states of counts of the address counter 11 in display and retrace line periods. The address counter 11, which continues counting also in the retrace line period, must discontinuously count the addresses at the beginning of a next display period, i.e., at the beginning of the next horizontal scanning line. A head address for generating such discontinuous addresses is generated every horizontal scanning line in the head address generation circuit 10 as hereinabove described, to be supplied to the address counter 11.
Referring to FIG. 19, zero is stored in the start address register 101 as a start address, while 80 is stored in the offset register 105 as an offset value. Thus, head addresses of first, second, third . . . horizontal scanning lines are changed as 0, 80, 160, . . .
Referring again to FIG. 13, the selector 21 selects and outputs the signal B which is supplied to its B input in response to the selection signal S in a mode of not vertically enlarging the screen. The signal B indicating a retrace line period is generated every horizontal scanning line, whereby the head address is changed every horizontal scanning line.
In a mode of vertically enlarging the screen, on the other hand, the selector 21 selects and outputs the signal from the AND gate 20, which is supplied to its A input, in response to the selection signal S. The output signal from the AND gate 20 is obtained by data-skipping the signal B at a prescribed rate, as shown in the timing chart of FIG. 16. Namely, the data skipping counter 19, which is a 2-bit counter, outputs the carry signal C every time its count value reaches 3, as shown in FIG. 16. The AND gate 20 is closed in response to the carry signal C, so that the signal B is data-skipped at this timing. Therefore, the head address which is generated by the head address generation circuit 10 remains unchanged. Namely, the head address in a preceding horizontal scanning line is employed as such also in a next horizontal scanning line.
Referring to FIG. 16, the head address generation circuit 10 outputs the same head address for fourth and fifth horizontal scanning lines. Therefore, the display memory 2 is supplied with the same address over two horizontal scanning lines, and the same data are read from the display memory 2 over the two horizontal scanning lines. Therefore, an original single line (the fourth horizontal scanning line in FIG. 16) is enlarged to two lines, to be displayed. Since the data skipping counter 19 is a 2-bit counter, such operation is caused at a rate of one line every four horizontal scanning lines. Therefore, the overall screen is vertically enlarged to 4/3 times the initial screen for display.
Since the data skipping counter 19 is reset by the signal LH indicating the final line of one frame, the same horizontal scanning line is thereafter continuously enlarged to two lines so far as the selection signal S is in an enlargement mode. FIG. 21 shows this state, in which the fourth horizontal scanning line of the original image is repeated in the fourth and fifth horizontal scanning lines in every frame.
The display controller 1 shown in FIG. 13 further comprises a display data latch 12, a shift register 13 and a color conversion table 14 as parts for transferring the data which are read from the display memory 2 to the display unit 3 The display memory 2 is formed by four RAMs for storing color signals R, B and G and a luminance signal I respectively, while the display data latch 12 and the shift register 13 are also formed by four latches and four shift registers which are provided in parallel with each other, in response thereto.
Output data (8 by 4 bits in total) from the respective RAMs of the display memory 2 are supplied to corresponding data inputs D of the display data latch 12 respectively. The output data from the display memory 2 are latched by the display data latch 12 in response to the clock CC which is supplied to a timing input T of the display data latch 12, as shown in a timing chart of FIG. 20. Output data from the display data latch 12 are supplied to a data input D of the shift register 13. The shift register 13 loads the output data of the display data latch 12 in response to a load signal PL which is supplied to its load input LD, and serially outputs the as-loaded data bitwise in response to a dot clock DS received in its timing input T, as shown in FIG. 20. Since the shift register 13 is formed by four registers, 4-bit (1 bit by 4) data are successively outputted. A 1-dot pixel is formed by the 4-bit data. Namely, 2.sup.4 =16 colors can be displayed every pixel.
The color conversion table 14 receives the 4-bit data from the shift register 13 in its address input A, and converts the same to 6-bit color image data VD to output the same. Namely, color data for 2.sup.6 =64 colors are previously set and 16 colors to be displayed are previously selected therefrom in the color conversion table 14, which selects/outputs the as-selected 16 colors in accordance with 4-bit address input. This color conversion table 14 increases the number of colors (color selection range) which can be displayed on the display unit 3
In the conventional display controller 1 having the aforementioned structure, horizontal scanning lines repeating the same display are fixed in all frames in the mode of vertically enlarging the screen, as shown in FIG. 21. When an oblique thin line is vertically enlarged, therefore, every frame presents a screen shown in FIG. 22 with steps appearing in the oblique line to cause indented appearance.
In order to solve this problem, there has been proposed a technique of passing an output from a color conversion table 14 through two line memories 51 and 52 which are connected in series with each other and operating outputs for two lines from the line memories 51 and 52 in an arithmetic unit 53 for smoothing the image, as shown in FIG. 23. However, this method requires the line memories 51 and 52 and the arithmetic unit 53, leading to complicatedness of the unit structure.